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january 2007 rev 6 1/49 1 m25p64 64 mbit, low voltage, serial flash memory with 50 mhz spi bus interface features 64 mbit of flash memory 2.7 v to 3.6 v single supply voltage spi bus compatible serial interface 50 mhz clock rate (maximum) v pp = 9 v for fast program/erase mode (optional) page program (up to 256 bytes) ? in 1.4 ms (typical) ? in 0.35 ms (typical with v pp = 9 v) sector erase (512 kbit) bulk erase (64 mbit) electronic signatures ? jedec standard two-byte signature (2017h) ? res instruction, one-byte, signature (16h), for backward compatibility hardware write protection: protected area size defined by three non-volatile bits (bp0, bp1 and bp2) more than 100 000 erase/program cycles per sector more than 20-year data retention packages ? ecopack? (rohs compliant) vdfpn8 (me) 8 6 mm (mlp8) so16 (mf) 300 mils width www.st.com
contents m25p64 2/49 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 chip select (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 hold (hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 write protect/enhanced program supply voltage (w/v pp ) . . . . . . . . . . . . 10 2.7 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.4 fast program/erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
m25p64 contents 3/49 6.4.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4.3 bp2, bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4.4 srwd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.6 read data bytes (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.7 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . 31 6.8 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.9 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.10 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.11 read electronic signature (res) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
list of tables m25p64 4/49 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5. read identification (rdid) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. power-up timing and vwi threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 10. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 11. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 12. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15. vdfpn8 (mlp8) 8-lead very thin dual flat package no lead, 8 6 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 16. so16 wide ? 16 lead plastic small outline, 300 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 17. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
m25p64 list of figures 5/49 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. vdfpn connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. so connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. write enable (wren) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. write disable (wrdi) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. read identification (rdid) instruction sequence and data-out sequence . . . . . . . . . . . . . 25 figure 11. read status register (rdsr) instruction sequence and data-out sequence . . . . . . . . . . 27 figure 12. write status register (wrsr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13. read data bytes (read) instruction sequence and data-out sequence . . . . . . . . . . . . . . 30 figure 14. read data bytes at higher speed (fast_read) instruction and data-out sequence . . . 31 figure 15. page program (pp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 16. sector erase (se) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 figure 17. bulk erase (be) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 18. read electronic signature (res) instruct ion sequence and data-out sequence . . . . . . . . 36 figure 19. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 20. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 21. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 22. write protect setup and hold timing during wrsr when srwd = 1 . . . . . . . . . . . . . . . . . 43 figure 23. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 24. output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 25. v pph timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 26. vdfpn8 (mlp8) 8-lead very thin dual flat package no lead, 8 6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 27. so16 wide ? 16 lead plastic small outline, 300 mils body width . . . . . . . . . . . . . . . . . . . . 46
description m25p64 6/49 1 description the m25p64 is a 64 mbit (8m x 8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed spi-compatible bus. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. an enhanced fast program/erase mode is available to speed up operations in factory environment. the device enters this mode whenever the v pph voltage is applied to the write protect/enhanced program supply voltage pin (w /v pp ). the memory is organized as 128 sectors, each containing 256 pages. each page is 256 bytes wide. thus, the whole memory can be vi ewed as consisting of 32768 pages, or 8388608 bytes. the whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction. in order to meet environmental requirements, st offers the m25p64 in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an st trademark. ecopack specifications are available at: www.st.com .
m25p64 description 7/49 figure 1. logic diagram figure 2. vdfpn connections 1. there is an exposed central pad on the underside of the vdfpn package. this is pulled, internally, to v ss , and must not be allowed to be connected to any other voltage or signal line on the pcb. 2. see section 11: package mechanical for package dimensions, and how to identify pin-1. table 1. signal names signal name function direction c serial clock input d serial data input input q serial data output output s chip select input w /v pp write protect/enhanced program supply voltage input hold hold input v cc supply voltage v ss ground ai07485b s v cc m25p64 hold v ss w/v pp q c d 1 ai08595b 2 3 4 8 7 6 5 d v ss c hold q sv cc w/v pp m25p64
description m25p64 8/49 figure 3. so connections 1. du = don?t use 2. see section 11: package mechanical for package dimensions, and how to identify pin-1. 1 ai07486c 2 3 4 16 15 14 13 du du du du v cc hold du du m25p64 5 6 7 8 12 11 10 9 w/v pp q v ss du du s d c
m25p64 signal description 9/49 2 signal description 2.1 serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). 2.2 serial data input (d) this input signal is used to transfer data serially into the device. it receives instructions, addresses, and the data to be programmed. values are latched on the rising edge of serial clock (c). 2.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) ch anges after the fa lling edge of serial clock (c). 2.4 chip select (s ) when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal program, erase or write status register cycle is in progress, the device will be in the standby power mode. driving chip select (s ) low selects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. 2.5 hold (hold ) the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold conditio n, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select (s ) driven low.
signal description m25p64 10/49 2.6 write protect/enhanced program supply voltage (w /v pp ) w /v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if the w /v pp input is kept in a low voltage range (0v to v cc ) the pin is seen as a control input. this input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the bp2, bp1 and bp0 bits of the status register). if v pp is in the range of v pph it acts as an additional power supply pin. in this case v pp must be stable until the program/erase algorithm is completed. 2.7 v cc supply voltage v cc is the supply voltage. 2.8 v ss ground v ss is the reference for the v cc supply voltage.
m25p64 spi modes 11/49 3 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: cpol=0, cpha=0 cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from th e falling edge of serial clock (c). the difference between the two modes, as shown in figure 5 , is the clock polarity when the bus master is in stand-by mode and not transferring data: c remains at 0 for (cpol=0, cpha=0) c remains at 1 for (cpol=1, cpha=1) figure 4. bus master and memory devices on the spi bus 1. the write protect (w /v pp ) and hold (hold ) signals should be driven, hi gh or low as appropriate. figure 4 shows an example of three devices connected to an mcu, on an spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, the other devices are high impedance. resistors r (represented in figure 4 ) ensure that the m25p64 is not selected if the bus master leaves the s line in the high impedance state. as the bus master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the bus master is reset), the clock line (c) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the s line is pulled high while the c line is pulled low (thus ensuring that s and c do not become high at the same time, and so, that the t shch requirement is met). the typical value of r is 100 k ? , assuming that the time constant r*c p (c p = parasitic capacitance of the bus line) is shorter than the time during which the bus master leaves the spi bus in high impedance. ai13792 spi bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w/v pp hold hold hold rr r v cc v cc v cc v cc v ss v ss v ss v ss r w/v pp w/v pp
spi modes m25p64 12/49 example: c p = 50 pf, that is r*c p = 5 s <=> the application must ensure that the bus master never leaves the spi bus in the high impedance state for a time period shorter than 5s. figure 5. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
m25p64 operating features 13/49 4 operating features 4.1 page programming to program one data byte, two instructions are required: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see page program (pp) and table 14: ac characteristics ). 4.2 sector era se and bulk erase the page program (pp) instruction allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved either a sector at a time, using the sector erase (se) instruction, or throughout the entire memory, using the bulk erase (be) instruction. this starts an internal erase cycle (of duration t se or t be ). the erase instruction must be preceded by a write enable (wren) instruction. 4.3 polling during a write, program or erase cycle a further improvement in the time to write status register (wrsr), program (pp) or erase (se or be) can be achieved by not waiting for the worst case delay (t w , t pp , t se , or t be ). the write in progress (wip) bit is provided in the status register so that the application program can monitor its value, polling it to establish wh en the previous write c ycle, program cycle or erase cycle is complete. 4.4 fast program/erase mode the fast program/erase mode is used to speed up programming/erasing. the device enters the fast program/erase mode during the page program, sector erase or bulk erase instruction whenever a voltage equal to v pph is applied to the w /v pp pin. the use of the fast program/erase mode requires specific operating conditions in addition to the normal ones (v cc must be within the normal operating range): the voltage applied to the w /v pp pin must be equal to v pph (see ta b l e 1 0 ) ambient temperature, t a must be 25c 10c, the cumulated time during which w /v pp is at v pph should be less than 80 hours
operating features m25p64 14/49 4.5 active power and standby power modes when chip select (s ) is low, the device is selected, and in the active power mode. when chip select (s ) is high, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the standby power mode. the device consumption drops to i cc1 . 4.6 status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. for a detailed description of the status register bits, see section 6.4: read stat us register (rdsr) .
m25p64 operating features 15/49 4.7 protection modes the environments where non-volatile memory devices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the m25p64 features the following data protection mechanisms: power on reset and an internal timer (t puw ) can provide protection against inadvertant changes while the power supply is outside the operating specification. program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ?power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion the block protect (bp2, bp1, bp0) bits allow part of the memory to be configured as read-only. this is the software protected mode (spm). the write protect (w /v pp ) signal allows the block protect (bp2, bp1, bp0) bits and status register write disable (srwd) bit to be protected. this is the hardware protected mode (hpm). table 2. protected area sizes status register content memory content bp2 bit bp1 bit bp0 bit protected area unprotected area 0 0 0 none all sectors (1) (128 sectors: 0 to 127) 1. the device is ready to accept a bulk erase instru ction if, and only if, all blo ck protect (bp2, bp1, bp0) are 0. 0 0 1 upper 64th (2 sectors: 126 and 127) lower 63/64ths (126 sectors: 0 to 125) 0 1 0 upper 32nd (4 sectors: 124 to 127) lower 31/32nds (124 sectors: 0 to 123) 0 1 1 upper sixteenth (8 sectors: 120 to 127) lower 15/16ths (120 sectors: 0 to 119) 1 0 0 upper eighth (16 sectors: 112 to 127) lower seven-eighths (112 sectors: 0 to 111) 1 0 1 upper quarter (32 sectors: 96 to 127) lower three-quarters (96 sectors: 0 to 95) 1 1 0 upper half (64 sectors: 64 to 127) lower half (64 sectors: 0 to 63) 1 1 1 all sectors (128 sectors: 0 to 127) none
operating features m25p64 16/49 4.8 hold condition the hold (hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. however, taking this signal low does not terminate any write status register, program or erase cycle that is currently in progress. to enter the hold condition, the device must be selected, with chip select (s ) low. the hold condition starts on the falling edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low (as shown in figure 6 ). the hold condition ends on the rising edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low. if the falling edge does not coincide with serial clock (c) being low, the hold condition starts after serial clock (c) next goes low. similarly, if the rising edge does not coincide with serial clock (c) being low, the hold condition ends after serial clock (c) next goes low. (this is shown in figure 6 ). during the hold conditio n, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. normally, the device is kept selected, with chip select (s ) driven low, for the whole duration of the hold condition. this is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. if chip select (s ) goes high while the device is in the hold condition, this has the effect of resetting the internal logic of the device. to restart communication with the device, it is necessary to drive hold (hold ) high, and then to drive chip select (s ) low. this prevents the device from going back to the hold condition. figure 6. hold condition activation ai02029d hold c hold condition (standard use) hold condition (non-standard use)
m25p64 memory organization 17/49 5 memory organization the memory is organized as: 8388608 bytes (8 bits each) 128 sectors (512kbits, 65536 bytes each) 32768 pages (256 bytes each). each page can be individually programmed (bits are programmed from 1 to 0). the device is sector or bulk erasable (bits are erased from 0 to 1) but not page erasable. figure 7. block diagram ai08520b hold s w/v pp control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder size of the read-only memory area c d q status register 00000h 7fffffh 000ffh
memory organization m25p64 18/49 table 3. memory organization sector address range 127 7f0000h 7fffffh 126 7e0000h 7effffh 125 7d0000h 7dffffh 124 7c0000h 7cffffh 123 7b0000h 7bffffh 122 7a0000h 7affffh 121 790000h 79ffffh 120 780000h 78ffffh 119 770000h 77ffffh 118 760000h 76ffffh 117 750000h 75ffffh 116 740000h 74ffffh 115 730000h 73ffffh 114 720000h 72ffffh 113 710000h 71ffffh 112 700000h 70ffffh 111 6f0000h 6fffffh 110 6e0000h 6effffh 109 6d0000h 6dffffh 108 6c0000h 6cffffh 107 6b0000h 6bffffh 106 6a0000h 6affffh 105 690000h 69ffffh 104 680000h 68ffffh 103 670000h 67ffffh 102 660000h 66ffffh 101 650000h 65ffffh 100 640000h 64ffffh 99 630000h 63ffffh 98 620000h 62ffffh 97 610000h 61ffffh 96 600000h 60ffffh 95 5f0000h 5fffffh 94 5e0000h 5effffh 93 5d0000h 5dffffh
m25p64 memory organization 19/49 92 5c0000h 5cffffh 91 5b0000h 5bffffh 90 5a0000h 5affffh 89 590000h 59ffffh 88 580000h 58ffffh 87 570000h 57ffffh 86 560000h 56ffffh 85 550000h 55ffffh 84 540000h 54ffffh 83 530000h 53ffffh 82 520000h 52ffffh 81 510000h 51ffffh 80 500000h 50ffffh 79 4f0000h 4fffffh 78 4e0000h 4effffh 77 4d0000h 4dffffh 76 4c0000h 4cffffh 75 4b0000h 4bffffh 74 4a0000h 4affffh 73 490000h 49ffffh 72 480000h 48ffffh 71 470000h 47ffffh 70 460000h 46ffffh 69 450000h 45ffffh 68 440000h 44ffffh 67 430000h 43ffffh 66 420000h 42ffffh 65 410000h 41ffffh 64 400000h 40ffffh 63 3f0000h 3fffffh 62 3e0000h 3effffh 61 3d0000h 3dffffh 60 3c0000h 3cffffh 59 3b0000h 3bffffh 58 3a0000h 3affffh table 3. memory organization (continued) sector address range
memory organization m25p64 20/49 57 390000h 39ffffh 56 380000h 38ffffh 55 370000h 37ffffh 54 360000h 36ffffh 53 350000h 35ffffh 52 340000h 34ffffh 51 330000h 33ffffh 50 320000h 32ffffh 49 310000h 31ffffh 48 300000h 30ffffh 47 2f0000h 2fffffh 46 2e0000h 2effffh 45 2d0000h 2dffffh 44 2c0000h 2cffffh 43 2b0000h 2bffffh 42 2a0000h 2affffh 41 290000h 29ffffh 40 280000h 28ffffh 39 270000h 27ffffh 38 260000h 26ffffh 37 250000h 25ffffh 36 240000h 24ffffh 35 230000h 23ffffh 34 220000h 22ffffh 33 210000h 21ffffh 32 200000h 20ffffh 31 1f0000h 1fffffh 30 1e0000h 1effffh 29 1d0000h 1dffffh 28 1c0000h 1cffffh 27 1b0000h 1bffffh 26 1a0000h 1affffh 25 190000h 19ffffh 24 180000h 18ffffh 23 170000h 17ffffh table 3. memory organization (continued) sector address range
m25p64 memory organization 21/49 22 160000h 16ffffh 21 150000h 15ffffh 20 140000h 14ffffh 19 130000h 13ffffh 18 120000h 12ffffh 17 110000h 11ffffh 16 100000h 10ffffh 15 0f0000h 0fffffh 14 0e0000h 0effffh 13 0d0000h 0dffffh 12 0c0000h 0cffffh 11 0b0000h 0bffffh 10 0a0000h 0affffh 9 090000h 09ffffh 8 080000h 08ffffh 7 070000h 07ffffh 6 060000h 06ffffh 5 050000h 05ffffh 4 040000h 04ffffh 3 030000h 03ffffh 2 020000h 02ffffh 1 010000h 01ffffh 0 000000h 00ffffh table 3. memory organization (continued) sector address range
instructions m25p64 22/49 6 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) after chip select (s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in ta bl e 4 . every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), read status register (rdsr), read identification (rdid) or read electronic signature (res) instruction, the shifted-in instruction sequence is followed by a data-out sequence. chip select (s ) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page program (pp), sector erase (se), bulk erase (be), write status register (wrsr), write enable (wren) or write disable (wrdi), chip select (s ) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (s ) must driven high when the number of clock pulses after chip select (s ) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected. table 4. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdid read identification 1001 1111 9fh 0 0 1 to 3 rdsr read status register 0000 0101 05h 0 0 1 to wrsr write status register 0000 0001 01h 0 0 1 read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to pp page program 0000 0010 02h 3 0 1 to 256 se sector erase 1101 1000 d8h 3 0 0 be bulk erase 1100 0111 c7h 0 0 0 res read electronic signature 1010 1011 abh 0 3 1 to
m25p64 instructions 23/49 6.1 write enable (wren) the write enable (wren) instruction ( figure 8 ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by drivin g chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. figure 8. write enable (wren) instruction sequence c d ai02281e s q 2 1 34567 high impedance 0 instruction
instructions m25p64 24/49 6.2 write disable (wrdi) the write disable (wrdi) instruction ( figure 9 ) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. the write enable latch (wel) bit is reset under the following conditions: power-up write disable (wrdi) instruction completion write status register (wrsr) instruction completion page program (pp) instruction completion sector erase (se) instruction completion bulk erase (be) instruction completion figure 9. write disable (wrdi) instruction sequence c d ai03750d s q 2 1 34567 high impedance 0 instruction
m25p64 instructions 25/49 6.3 read identification (rdid) the read identification (rdid) in struction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. the manufacturer identification is assigned by jedec, and has the value 20h for stmicroelectronics. the device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (17h). any read identification (rdid) instruction while an erase or pr ogram cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select (s ) low. then, the 8-bit instruction code for the instruction is shifted in. this is follow ed by the 24-bit device identification, stored in the memory, being shifted out on serial data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 10 . the read identification (rdid) instruction is terminated by dr iving chip select (s ) high at any time during data output. when chip select (s ) is driven high, the device is put in the standby power mode. once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. figure 10. read identification (rdid) instruction sequence and data-out sequence table 5. read identification (rdid) data-out sequence manufacturer identification device identification memory type memory capacity 20h 20h 17h c d s 2 1 3456789101112131415 instruction 0 ai06809b q manufacturer identification high impedance msb 15 1413 3210 device identification msb 16 17 18 28 29 30 31
instructions m25p64 26/49 6.4 read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of thes e cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 11 . the status and control bits of the status register are as follows: 6.4.1 wip bit the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to 1, such a cycle is in pr ogress, when reset to 0 no such cycle is in progress. 6.4.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase instruction is accepted. 6.4.3 bp2, bp1, bp0 bits the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. these bits are written with the write status register (wrsr) instruction. when one or more of the block protect (bp2, bp1, bp0) bits is set to 1, the relevant memory area (as defined in ta bl e 2 ) becomes protected against page program (pp) and sector erase (se) instructions. the block protect (bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not been set. the bulk erase (be) instruction is executed if, and only if, all block protect (bp2, bp1, bp0) bits are 0. table 6. status register format b7 b0 srwd 0 0 bp2 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit
m25p64 instructions 27/49 6.4.4 srwd bit the status register write disable (srwd) bit is operated in conjunction with the write protect (w /v pp ) signal. the status register write disable (srwd) bit and write protect (w /v pp ) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w /v pp ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. figure 11. read status register (rdsr) instruction sequence and data-out sequence c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
instructions m25p64 28/49 6.5 write status register (wrsr) the write status register (wrsr) instruction a llows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruct ion is entered by driving chip select (s ) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 12 . the write status register (wrsr) instruction has no effect on b6, b5, b1 and b0 of the status register. b6 and b5 are always read as 0. chip select (s ) must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed write stat us register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress , the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in ta b l e 2 . the write status register (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w /v pp ) signal. the status register write disable (srwd) bit and write protect (w /v pp ) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hardware protected mode (hpm) is entered. the protection features of the device are summarized in ta bl e 7 . table 7. protection modes w /v pp signal srwd bit mode write protection of the status register memory content protected area (1) 1. as defined by the values in the block protect (bp2 , bp1, bp0) bits of the status register, as shown in table 2 . unprotected area (1) 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the srwd, bp2, bp1 and bp0 bits can be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the srwd, bp2, bp1 and bp0 bits cannot be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions
m25p64 instructions 29/49 when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) in struction, regardless of the whether write protect (w /v pp ) is driven high or low. when the status register write disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w /v pp ): if write protect (w /v pp ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. if write protect (w /v pp ) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp2, bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: by setting the status register write disable (srwd) bit after driving write protect (w /v pp ) low or by driving write protect (w /v pp ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect/ (w /v pp ) high. if write protect/ (w /v pp ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp2, bp1, bp0) bits of the status register, can be used. figure 12. write status register (wrsr) instruction sequence c d ai02282d s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
instructions m25p64 30/49 6.6 read data bytes (read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 13 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes (read) instruction, while an erase, program or write cycl e is in progress, is rejected without having any effects on the cycle that is in progress. figure 13. read data bytes (read) instruction sequence and data-out sequence 1. address bit a23 is don?t care. c d ai03748d s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
m25p64 instructions 31/49 6.7 read data bytes at higher speed (fast_read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes at higher speed (f ast_read) instruction is followed by a 3-byte address (a23- a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 14 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_rea d) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes at higher speed (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 14. read data bytes at higher speed (fast_read) instruction and data-out sequence 1. address bit a23 is don?t care. c d ai04006 s q 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24 bit address 0 c d s q 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35
instructions m25p64 32/49 6.8 page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significan t bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see ta b l e 1 4 : ac characteristics ). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cy cle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page progra m cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see ta b l e 2 and ta bl e 3 ) is not executed.
m25p64 instructions 33/49 figure 15. page program (pp) instruction sequence c d ai04082b s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb
instructions m25p64 34/49 6.9 sector erase (se) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (s ) low, followed by the instruction code, and three address bytes on serial data input (d). any address inside the sector (see ta b l e 3 ) is a valid address for the sector erase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 16 . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in pr ogress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see ta b l e 2 and ta bl e 3 ) is not executed. figure 16. sector erase (se) instruction sequence 1. address bit a23 is don?t care. 24 bit address c d ai03751d s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
m25p64 instructions 35/49 6.10 bulk erase (be) the bulk erase (be) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the bulk erase (be) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial da ta input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 17 . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the bulk erase instruction is not executed. as soon as chip select (s ) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiate d. while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the bulk erase (be) instruction is executed only if all block protect (bp2, bp1, bp0) bits are 0. the bulk erase (be) instruction is ignored if one, or more, sectors are protected. figure 17. bulk erase (be) instruction sequence c d ai03752d s 2 1 34567 0 instruction
instructions m25p64 36/49 6.11 read electronic signature (res) the instruction is used to read, on serial data output (q), the old-style 8-bit electronic signature, whose value for the m25p64 is 16h . please note that this is not the same as, or even a subset of, the jedec 16-bit electronic signature that is read by the read identifier (rdid) instruction. the old-style electronic signature is supported for reas ons of backward compatibility, only, and should not be used for new designs. new designs should, instead, make use of the jedec 16-bit electronic signature, and the read identifier (rdid) instruction. the device is first selected by driving chip select (s ) low. the instruction code is followed by 3 dummy bytes, each bit being latched-in on serial data input (d) during the rising edge of serial clock (c). then, the old-style 8-bit electronic signature, stored in the memory, is shifted out on serial data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 18 . the read electronic signature (res) instruction is terminated by driving chip select (s ) high after the electronic signature has been read at least once. sending additional clock cycles on serial clock (c ), while chip select (s ) is driven low, cause the electronic signature to be output repeatedly. when chip select (s ) is driven high, the device is put in the standby power mode. once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. driving chip select (s ) high after the 8 - bit instruction byte has been received by the device, but before the whole of the 8-bit electronic sign ature has been transmitted for the first time, still ensures that the device is put into st andby power mode. once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. figure 18. read electronic signature (res) instruction sequence and data-out sequence 1. the value of the 8-bit electronic signature, for the m25p64, is 16h. c d ai04047c s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 765432 0 1 high impedance electronic signature out instruction 3 dummy bytes 0 msb msb
m25p64 power-up and power-down 37/49 7 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: v cc (min) at power-up, and then for a further delay of t vsl v ss at power-down a safe configuration is provided in section 3: spi modes . to avoid data corruption and inadvertent write operations during power-up, a power on reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the power on reset (por) threshold voltage, v wi ? all operations are disabled, and the device does not resp ond to any instruction. moreover, the device ignores all write enable (wren), page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instructions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write status register, program or erase instructions should be sent until the later of: t puw after v cc passed the v wi threshold t vsl after v cc passed the v cc (min) level these values are specified in ta bl e 8 . if the delay, t vsl , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instructions even if the t puw delay is not yet fully elapsed. at power-up, the device is in the following state: the device is in the standby power mode the write enable latch (wel) bit is reset the write in progress (wip) bit is reset normal precautions must be taken for su pply rail decoupling, to stabilize the v cc supply. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 100 nf). at power-down, when v cc drops from the operating voltage, to below the power on reset (por) threshold voltage, v wi , all operations are disabled and the device does not respond to any instruction. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result.). power up sequencing for fast program/erase mode: v cc should attain v ccmin before v pph is applied.
power-up and power-down m25p64 38/49 figure 19. power-up timing 1. these parameters ar e characterized only. table 8. power-up timing and vwi threshold symbol parameter min. max. unit t vsl (1) v cc (min) to s low 30 s t puw (1) time delay to write instruction 1 10 ms v wi (1) write inhibit voltage 1.5 2.5 v v cc ai04009c v cc (min) v wi reset state of the device chip selection not allowed program, erase and write commands are rejected by the device tvsl tpuw time read access allowed device fully accessible v cc (max)
m25p64 initial delivery state 39/49 8 initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). 9 maximum rating stressing the device outside the ratings listed in ta bl e 9 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroe lectronics sure program and other relevant quality documents. table 9. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020c (for smal l body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu c v io input and output voltage (with respect to ground) ?0.5 v cc + 0.6 v v cc supply voltage ?0.2 4.0 v v pp fast program/erase voltage ?0.2 10.0 v v esd electrostatic discharge voltage (human body model) (2) 2. jedec std jesd22-a114a (c1=100 pf, r1 = 1500 ? , r2 = 500 ? ). ?2000 2000 v
dc and ac parameters m25p64 40/49 10 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. 1. output hi-z is defined as the point where data out is no longer driven. figure 20. ac measurement i/o waveform 1. sampled only, not 100% tested, at t a = 25 c and a frequency of 20 mhz. table 10. operating conditions symbol parameter min. typ max. unit v cc supply voltage 2.7 3.6 v v pph supply voltage on w /v pp pin for fast program/erase mode 8.5 9.5 v t a ambient operating temperature ?40 85 c t avpp ambient operating te mperature for fast program/erase mode 15 25 35 c table 11. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input timing refer ence voltages 0.3v cc to 0.7v cc v output timing reference voltages v cc / 2 v table 12. capacitance symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0 v 8 pf c in input capacitance (other pins) v in = 0 v 6 pf ai07455 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels 0.5v cc
m25p64 dc and ac parameters 41/49 table 13. dc characteristics symbol parameter test condition (in addition to those in table 10 ) min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 100 a i cc3 operating current (read) c = 0.1v cc / 0.9.v cc at 50 mhz, q = open 8ma c = 0.1v cc / 0.9.v cc at 20 mhz, q = open 4ma i cc4 operating current (pp) s = v cc 15 ma i cc5 operating current (wrsr) s = v cc 20 ma i cc6 operating current (se) s = v cc 20 ma i cc7 operating current (be) s = v cc 20 ma i ccpp operating current for fast program/erase mode s = v cc , v pp = v pph 20 ma i pp v pp operating current in fast program/erase mode s = v cc , v pp = v pph 20 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.2 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 a v cc ?0.2 v
dc and ac parameters m25p64 42/49 1. t ch + t cl must be greater than or equal to 1/ f c (max) 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wr sr instruction when srwd is set at 1. 5. when using the page program (pp) inst ruction to program consecutive bytes, optimized timings are obtained with one sequence including all the byte s versus several sequences of only a few bytes. (1 n 256). 6. v pph should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. table 14. ac characteristics test conditions specified in table 10 and table 11 symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, res, wren, wrdi, rdid, rdsr, wrsr d.c. 50 mhz f r clock frequency for read instructions d.c. 20 mhz t ch (1) t clh clock high time 9 ns t cl (1) t cll clock low time 9 ns t clch (2) clock rise time (3) (peak to peak) 0.1 v/ns t chcl (2) clock fall time (3) (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 100 ns t shqz (2) t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 5 ns t chhh hold hold time (relative to c) 5 ns t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx (2) t lz hold to output low-z 8 ns t hlqz (2) t hz hold to output high-z 8 ns t whsl (4) write protect setup time 20 ns t shwl (4) write protect hold time 100 ns t vpphsl (6) enhanced program supply voltage high to chip select low 200 ns t w write status register cycle time 5 15 ms t pp (5) page program cycle time (256 bytes) 1.4 5ms page program cycle time (n bytes) 0.4+ n*1/256 page program cycle time (v pp = v pph ) (256 bytes) 0.35 ms t se sector erase cycle time 1 3 s sector erase cycle time (v pp = v pph )0.5s t be bulk erase cycle time 68 160 s bulk erase cycle time (v pp = v pph )35160s
m25p64 dc and ac parameters 43/49 figure 21. serial input timing figure 22. write protect setup and hold timing during wrsr when srwd = 1 c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c d s q high impedance w/v pp twhsl tshwl ai07439b
dc and ac parameters m25p64 44/49 figure 23. hold timing figure 24. output timing figure 25. v pph timing c q ai02032 s d hold tchhl thlch thhch tchhh thhqx thlqz c q ai01449e s lsb out d addr lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv s c d w/v pp v pph pp, se, be ai12092 tvpphsl end of pp, se or be (identified by wpi polling)
m25p64 package mechanical 45/49 11 package mechanical figure 26. vdfpn8 (mlp8) 8-lead very thin dual flat package no lead, 8 6 mm, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 15. vdfpn8 (mlp8) 8-lead very thin dual flat package no lead, 8 6 mm, package mechanical data symbol millimeters inches typ min max typ min max a 0.85 1.00 0.0335 0.0394 a1 0.00 0.05 0.0000 0.0020 b 0.40 0.35 0.48 0.0157 0.0138 0.0189 d 8.00 0.3150 d2 5.16 (1) 1. d2 max must not exceed (d ? k ? 2 l). 0.2031 ddd 0.05 0.0020 e 6.00 0.2362 e2 4.80 0.1890 e1.27? ?0.0500? ? k 0.82 0.0323 l 0.50 0.45 0.60 0.0197 0.0177 0.0236 l1 0.15 0.0059 n8 8 d e vdfpn-02 a e e2 d2 l b l1 a1 ddd k
package mechanical m25p64 46/49 figure 27. so16 wide ? 16 lead plastic small outline, 300 mils body width 1. drawing is not to scale. table 16. so16 wide ? 16 lead plastic small outline, 300 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 10.10 10.50 0.398 0.413 e 7.40 7.60 0.291 0.299 e1.27? ?0.050? ? h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.40 1.27 0.016 0.050 0 8 0 8 ddd 0.10 0.004 e 16 d c h 1 8 9 so-h l a1 a ddd a2 b e h x 45?
m25p64 part numbering 47/49 12 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 17. ordering information scheme example: m25p64 ? v mf 6 t p device type m25p = serial flash memory for code storage device function 64 = 64 mbit (8m x 8) operating voltage v = v cc = 2.7 v to 3.6 v package mf = so16 (300 mil width) me = vdfpn8 8 6 mm (mlp8) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow option blank = standard packing t = tape and reel packing plating technology p or g = ecopack? (rohs compliant)
revision history m25p64 48/49 13 revision history table 18. document revision history date revision changes 28-apr-2003 0.1 target specification document written in brief form 15-may-2003 0.2 target specificat ion document written in full 20-jun-2003 0.3 8x6 mlp8 and so16(300 mil) packages added 18-jul-2003 0.4 t pp , t se and t be revised 02-sep-2003 0.5 voltage supply range changed 19-sep-2003 0.6 table of contents, warning about exposed paddle on mlp8, and pb-free options added 17-dec-2003 0.7 value of t vsl (min) v wi , t pp (typ) and t be (typ) changed. mlp8 package removed. 15-nov-2004 1.0 document status pr omoted from target specific ation to preliminary data. 8x6 mlp8 package added. minor wording changes. 24-feb-2005 2.0 deep power-down mode removed from datasheet ( figure 18: read electronic signature (res) instru ction sequence and data-out sequence modified and tres1 and tres2 removed from table 14: ac characteristics ). so16 wide package specific ations updated. end timing line of t shqz modified in figure 24: output timing . figures moved below the corresponding instructions in the instructions section. 23-dec-2005 3.0 updated page program (pp) instructions in page programming , page program (pp) and table 14: ac characteristics . fast program/erase mode added and power-up specified for fast program/erase mode in power-up and power-down section. w pin changed to w /v pp . (see write protect/enhanced program supply voltage (w/v pp ) description). note 2 inserted below figure 26 blank option removed under plating technology . t vpphsl added to table 14: ac characteristics and figure 25: v pph timing inserted. all packages are ecopack? compliant. document status promot ed from preliminary data to full datasheet status. 16-feb-2006 4.0 vdfpn8 (mlp8) package specifications updated (see section 11: package mechanical ). 07-sep-2006 5 figure 4: bus master and memory devices on the spi bus modified. i cc1 maximum value updated in table 13: dc characteristics . 19-jan-2007 6 hardware write protection feature added to features on page 1 . v cc supply voltage and v ss ground descriptions added. figure 4: bus master and memory devices on the spi bus updated and explanatory paragraph added. at power-up the write in progress (wip) bit is reset . v io max modified and t lead added in table 9: absolute maximum ratings . small text changes. note 1 added to table 15: vdfpn8 (mlp8) 8-lead very thin dual flat package no lead, 8 6 mm, package mechanical data .
m25p64 49/49 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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